Field of the Invention
This invention relates to array architecture of Non-Volatile Memory (NVM) semiconductor cell devices. In particular, the innovative Field Sub-bitline NOR (FSNOR) flash array is configured with multiple NVM semiconductor cell devices, where the drain electrodes of multiple NVM cell pairs in a column are connected together to form two field side sub-bitlines and the common source electrodes of the multiple NVM cell pairs in the column are connected to form a single common source line, and the control gates of multiple NVM cell pairs in rows form the wordlines.
Description of the Related Art
Non-Volatile Memory (NVM) semiconductor, and particularly Electrically Erasable, Programmable Read-Only Memories (EEPROM), exhibit wide spread applicability in a range of electronic equipment from computers, to telecommunication hardware, to consumer appliances. In general, EEPROM serves a niche in the NVM space as a mechanism for storing firmware and data that can be kept even with power off and can be altered as needed.
Non-volatile data represented by the states of threshold voltages (devices' on/off voltages) is stored in EEPROM devices by modulating devices' threshold voltages through the injection of charge carriers into the charge-storage layer of EEPROM devices. For example, with respect to an N-channel EEPROM device, an accumulation of electrons in the floating gate, or in a charge storage dielectric layer, or in a layer of embedded nano-crystals above the channel region, causes the device to exhibit a relatively high threshold voltage.
Flash EEPROM may be regarded as specifically configured EEPROM devices into cell array that may be erased only on a global or sector-by-sector basis. Flash EEPROM arrays are also categorized into NOR flash and NAND flash according to the configurations of memory cell connections in the flash arrays. The conventional NOR flash array connects cell devices in parallel-connected pairs 10 in FIG. 1, where rows of common source electrodes of the paired cell devices 10 are connected to form multiple horizontal common source lines CS and columns of drain electrodes of the paired cell devices 10 are connected to form multiple vertical bitlines, respectively. As the cell device schematic for an “M×N” NOR flash array shown in FIG. 1, each wordline running in x-direction contains “M” NVM cells with the drain electrodes 12 of the NOR cell pairs 10 vertically connected to form bitlines Bi for i=1, . . . M, and each bitline running in y-direction is attached with “N” drain electrodes of the NVM cells. The common source electrodes 11 of rows of NOR cell pairs 10 in the array are horizontally connected to form the common source lines CS. When a wordline is selected, the entire “M” NVM cells of the selected wordline are activated. On the other hand, the NVM cells of the unselected wordlines in the array are electrically detached from the “M” bitlines. The electrical responses at the drain electrodes of the selected “M” NVM cells can be detected through their attached “M” bitlines. Since the applied electrical biases and NVM signals are directly in contact with the drain electrodes of the selected NVM cells in NOR-type flash array without passing any other NMV devices, the read and write access speed are faster and the operation voltages are lower for NOR-type flash array in comparison with NAND-type flash array.
The NAND-type flash array connects the NVM cells in series. Unlike the NOR type array with the configuration of source electrode-to-source electrode connection and drain electrode-to-drain electrode connection, NAND-type flash array link the drain electrode of an NVM cell to the source electrode of its next neighboring cell. Usually, the numbers of NVM cells linked in one single NAND string 20 in FIG. 2 are from 8 cells to 128 cells depending on the generations of the process technology nodes. In FIG. 2, the schematic for an “M×N” NAND flash array, the array contains “q*M” NAND cell strings 20 and each NAND cell string 20 contains “p” NVM cells (p=8˜128) and one selection gate to connect the string to the main bitline. Each bitline has “q” NAND cell strings 20 attached. Thus the total NVM cells attached to a single main bitline is p*q=N for an “M×N” NAND array. Since the source electrode and the drain electrode of NVM cells are overlapped each other in the NAND cell string, the NVM cells have no contacts in between the linked NVM cells except one contact 21 placed at the end of the cell string for connecting the NAND string to the main bitline. Usually, a single main bitline connects several NAND strings 20 in y-direction and common source lines CS run in x-direction in the NAND flash array. In contrast, each pair of NVM cells in NOR-type array does have one contact 11 for connecting the cell's two drain electrodes (one drain electrode equivalently sharing a half contact) to the main bitline. A NOR-type flash array is equivalently to a NAND-type array with p=1. Typically, the NOR-type NVM cell sizes including the area for a single contact 11 in a NOR flash array are 9˜10 F2 and the NAND-type NVM cell sizes without a contact area in a NAND flash array can achieve the minimum cell area of 4 F2 respectively, where F is minimum feature size for a process technology node. Therefore, the chip areas of NAND type flash arrays are smaller than those of the NOR type flash arrays (˜40% to ˜50% smaller) for the same memory bits with the same process technology node. In term, the smaller cell array areas for NAND flash would have the advantage of lower manufacturing cost for the same bit storage capacity.
Making NOR flash array to be cost competitive as NAND flash array for the same 4F2 memory cell sizes, we disclosed the NOR flash array using the NVM cell semiconductor devices fabricated with the conventional flash process technology in U.S. Pat. Nos. 8,415,721 B2 and 8,716,138 B2 (the disclosure of which are incorporated herein by reference in their entirety). In the disclosures as shown in FIG. 3, the NOR cell pairs 30 of NVM semiconductor devices in FIG. 3 are arranged by rotating 90° of the conventional NOR cell pairs 10 shown in FIG. 1. The drain and source electrodes of the NOR cell pairs 30 form the diffusion sub-bitlines 31 separated by trench field isolation. By twisting the diffusion sub-bitlines along the trench field isolation by a fractional pitch, the diffusion sub-bitlines are able to link their sub-feature diffusion lines (whose features are smaller than the minimum feature F) to the full feature diffusion areas, where full-feature contacts 32 can be landed on. Through the contacts 32 attached to the main bitlines Bi for i=1, . . . , M, in FIG. 3, the electrical signals can be picked up from the selected NVM cell devices and the voltage biases can be applied to drain electrodes of the selected NVM cell devices without passing any other NVM cell devices as the NAND flash. For the FSNOR flash array 300 in FIG. 3, multiple rows (said 8˜128 rows) of NOR cell pairs 30 are connected with diffusion sub-bitlines to form a NOR flash sector 300s. The main metal bitlines globally connect multiple sectors through the multiple contacts 32 to form a bank of NOR flash array 300. Since the extension of multiple sectors in a bank increases the bitline (multiple sub-bitlines+main bitline), capacitance C and resistance R, the electrical signals and voltage biases passing through the bitline to the drain electrodes of the selected NVM devices would be slow and degraded due to the large bitline RC time delay and IR (current-resistance) drops, respectively. Furthermore, the excessive numbers of the unselected NVM devices forming the multiple sector sub-bitlines attached to the single main bitline also increase the bitline leakage currents, i. e., the numbers of unselected cell devices attached to the main bitline multiplied by cell's junction/channel-diffusion leakage current, resulting in high bitline leakage current noise levels for read operation, and significant applied drain voltage bias drops to the drain electrodes of the selected NVM cell devices in programming operation. For those reasons, the numbers of multiple sectors extended in a bank has to be capped for minimum signal/noise ratio and the applying drain voltage bias integrity.
In order to be extendable for the numbers of sectors attached to the single main metal bitlines in a bank, not limited by the above reasons, and reduce the line resistance from the larger resistance of sub-bitlines to the smaller resistance of common source lines, we has disclosed a new type of 4F2 FSNOR flash array separated by sectors with the even/odd sub-bitline selections to the global main bitlines for the even/odd number NVM cell devices of the NVM cell pairs and the low resistance global common source lines. In the new FSNOR array architecture of the invention, one and only one selected NVM device is electrically connected to the single global main metal bitline for the accessing operations of read and programming such that the selected NVM cell devices are fully immune from the interferences of other unselected NVM cell devices in the array. This interference immunity for the new FSNOR flash array of the invention is proven to be much better performance on NVM signal/noise ratio, applying drain voltage bias integrity, and programming disturbance to the neighboring cells than any other existing flash arrays.